1. Field of the Invention
The present invention relates to a system simulator, a simulation method and a simulation program. More particularly, the present invention relates to a technique for simulating such a system that a bus master and a bus slave are connected to each other through a bus.
2. Description of the Related Art
Conventionally, as an apparatus to which a microprocessor is applied, such a system that a bus master (hereafter, merely referred to as “Master”) and a bus slave (hereafter, merely referred to as “Slave”) are connected to each other through a bus is known. The software applied to this system is typically developed by using the hardware after the hardware environment to operate the software is prepared, in other words, after the completion of the development of the hardware.
However, in above-mentioned conventional developing method, a long time is required to develop the system. Therefore, recently, in order to reduce the developing period, such a developing method is employed that the development of the software is carried out on a system simulator. By employing this method, the development of the software can be carried out in parallel with the development of the hardware. As a result, the developing period can be reduced.
FIG. 1 shows a configuration of a conventional system simulator (hereafter, referred to as “system simulator according to a first conventional technique”) used for the development of the software. This system simulator comprises a first master, a second master, a slave and a manager.
The first master is a simulator composed of a program for simulating an operation of a device used as a master such as CPU and DMA. The second master is another simulator composed of a program for simulating another device used as the master. The slave is a simulator composed of a program for simulating a peripheral circuit used as a slave such as a timer, a serial input output port, a general input output port and a memory. The manager is the control program for operating the first master, the second master and the slave in synchronization with each other.
The system simulator according to the first conventional technique having the above-mentioned configuration is used to verify the correctness of the program incorporated in each of the first master, the second master and the slave.
In the system simulator according to this first conventional technique, the simulation is advanced while the manager performs a function call to the first master, the second master and the slave, sequentially. In detail, the manager firstly performs the function call to the first master. Accordingly, the first master executes a process corresponding to one clock. For example, if the target of the function call is an instruction to be completed in one clock, the execution of the instruction is carried out. After that, the control is returned back to the manager. If the target of the function call is an instruction requiring a plurality of clocks, the control is returned back to the manager after the completion of a process corresponding to the one clock.
Next, the manager performs the function call to the second master, similarly to the above-mentioned case. Continuously, the manager performs the function call to the slave. After that, the simulation is advanced by that the function call to the first master □ the second master □ the slave □ the first master □ . . . is cyclically performed. It should be noted that, if the target of the function call is the instruction requiring the plurality of clocks, the execution of the instruction is completed by executing the plurality of function calls to the target.
As described above, the first master, the second master and the slave sequentially execute the process corresponding to the one clock for each execution of the function call from the manager. Thus, the first master, the second master and the slave are operated as if they are in synchronization with the clock. That is, it can be considered that the first master, the second master and the slave are operated such that the operational timings are given from the manager. Hence, it is possible to carry out the simulation in which the operational timings are considered.
FIG. 2 shows a configuration of another conventional system simulator (hereafter, referred to as “system simulator according to a second conventional technique”) using a semaphore as a synchronizing mechanism for synchronizing a plurality of simulators with each other. The system simulator according to the second conventional technique always carries out a multi-thread operation.
The system simulator according to this second conventional technique comprises a first master, a second master, a slave, a manager and a bus. The first master, the second master, the slave and the manager have the functions similar to those of the above-mentioned conventional system simulator according to the first conventional technique, respectively. The bus is the simulator for simulating the operation of the bus when the first master and the second master access the slave.
In FIG. 2, symbols “□” in the first master, the second master, the manager and the bus denote the semaphores. A symbol “P” denotes an execution of a post, a symbol “W” denotes an execution of a wait, and a symbol “T” denotes an execution of a try wait, respectively. The try wait is a function of carrying out an inquiry to the bus. The system simulator according to this second conventional technique is controlled so as to activate only one of the first master, the second master and the manager at the same time.
Basically, the manager performs the post “P” to the semaphore of the first master and the second master (hereafter, they may be merely collectively referred to as “master”), and thereby activates the thread of the master, and the manager itself enters in the wait “W” state. Also, the master performs the post “P” to the semaphore of the manager, and thereby returns the control back to the manager, and the master itself enters in the wait “W” state. The slave is activated when the manager performs the function call to the slave, similarly to the system simulator according to the first conventional technique.
The actual operations of the system simulator according to this second conventional technique will be described below with reference to FIGS. 3 to 5.
FIG. 3 is an explanatory diagram showing the transfer operation between the manager and the first master. Dotted lines indicate the flow of the control. The manager firstly performs the post to the semaphore of the first master, and the manager itself enters in the wait state. This post operation activates the thread of the first master being in the wait state, and the try wait is performed to the semaphore of the bus. Then, if this try wait is unsuccessful, the first master performs the post to the semaphore of the manager, and the first master enters in the wait state.
FIG. 4 is an explanatory diagram showing the transfer operation between the manager and the second master. Dotted lines indicate the flow of the control. As mentioned above, when the control is transferred to the manager by that the first master performs the post to the semaphore of the manager, the manager then performs the post to the semaphore of the second master, and the manager itself enters in the wait state. This post operation activates the thread of the second master being in the wait state, and the try wait is performed to the semaphore of the bus. Then, if this try wait is unsuccessful, the second manager performs the post to the semaphore of the manager, and the second master enters in the wait state.
FIG. 5 is an explanatory diagram showing the transfer operation between the manager and the slave. Dotted lines indicate the flow of the control. As mentioned above, when the control is transferred to the manager by that the second master performs the post to the semaphore of the manager, the manager then performs the function call to the slave. If the slave becomes at a state responsible to an access request from the first master and the second master, the slave performs the post to the semaphore of the bus. This implies that the next try waits perfumed by the first and second masters are successful. After that, the control is returned from the slave to the manager. After that, the above-mentioned operations are repeated.
As mentioned above, the first and second masters, while carrying out the thread switching, sequentially execute the process corresponding to the one clock in each thread, and the slave executes the process corresponding to the one clock for each performance of the function call from the manager. Thus, the first master, the second master and the slave are operated as if they are in synchronization with the clock. Hence, it is possible to carry out the simulation in which the operational timings are considered.
In this system simulator according to the second conventional technique, when the master accesses the slave, even if an access blocking occurs, namely, even if the master fails in the try wait of the bus, there is no case that the master continues to wait for the response. Thus, there is no case that this system simulator gets into a dead lock state.
As a related art, Japanese Laid Open Patent Application (JP-A-Heisei 11-296408) discloses a software logic simulator for an assembled apparatus. This software logic simulator can attain a simulation for hardware by a plurality of applications, and carry out a linkage operation between them, and thereby simplify the description of the hardware operations, and further improve a debugging efficiency of software. According to this simulator, if the debugging operation is performed in linkage between the hardware simulator and the software, it is possible to solve the problems that the speed of the simulation of the hardware operation is very slow and that the description of the hardware has a defect.
However, the system simulator according to the first conventional technique has the following problem. That is, the program of the master includes the instruction to access to the slave. When the master executes this instruction, if the slave can respond to it within a time corresponding to the one clock, there is no problem. However, most of the slaves require several clocks for the response. The above mentioned phenomenon that the slave can not immediately respond to the access from the master is referred to as “Access Blocking”. The access blocking includes a read access blocking and a write access blocking.
If the access blocking occurs, the master enters in the waiting state for waiting the response from the slave, and the control is not returned back to the manager. Consequently, the clock is not supplied to the slave. Thus, the master still continues the waiting state, and the system simulator gets into the dead lock state.
This problem can be solved by changing the specification of the slave on the system simulator such that the response is returned in one clock. However, in this approach, because the specification of the slave on the system simulator differs from that of the actual slave, it is impossible to carry out the simulation by considering the operation timing. The above-mentioned problem can be also solved by designing the program of the master such that the master being in the waiting state for waiting the response from the slave forcedly returns the control to the manager. However, in this approach, it is necessary to re-design the conventional program of the master. Moreover, when it is re-designed, the structure of the program of the master becomes complex. Thus, the development of the program of the master requires a large number of steps.
The system simulator according to the second conventional technique does not get into the dead lock state. However, it has the following problem. That is, in this system simulator, the thread switching is always performed under the control of a thread controller. Thus, this thread switching causes an occurrence of a loss time. The amount of the loss time is determined depending on the program installed in the master. According to the measurement by the inventors of the present invention, the simulation time of the system simulator according to the second conventional technique is equal to about 20 to 40 times the simulation time of the system simulator according to the first conventional technique.